1. Field of the Invention
The invention relates to a method and apparatus for clock phase locking in a phase-locked loop, more particularly to a method and apparatus for enabling fast clock phase locking in a phase-locked loop.
2. Description of the Related Art
Referring to FIG. 1, a typical rewritable digital versatile disc (hereinafter referred to as DVDRAM) 1 is shown to include a plurality of adjacent header regions 12 and record regions 11. Each header region 12 precedes a corresponding record region 11, and includes package headers and packet headers that describe data recorded in the corresponding record region 11. When reading binary data of digital signals recorded in the DVDRAM 1, clock phase locking of the digital signals must be performed first through a phase-locked loop. Referring to FIG. 2, a typical phase-locked loop 2 is shown to include a phase detector 21, a charge pump 22 coupled to the phase detector 21, a loop filter 23 coupled to the charge pump 22, a voltage controlled oscillator (VCO) 24 coupled to the loop filter 23, and a frequency divider 25 interconnecting the voltage controlled oscillator 24 and the phase detector 21. During operation, an input digital signal (IN) associated with the DVDRAM 1, together with a reference clock signal (CLK) from the frequency divider 25, are provided to the phase detector 21. When the reference clock signal (CLK) overruns the input digital signal (IN), the phase detector 21 either provides ascending pulses (UP) with narrower widths or descending pulses (DN) with wider widths to the charge pump 22. At this time, the charge pump 22 generates a positive current output (Icp) that is integrated by the loop filter 23 to result in a descending voltage (Vct) for controlling the voltage controlled oscillator 24 to lower the frequency of the reference clock signal (CLK) generated by the frequency divider 25. On the other hand, when the reference clock signal (CLK) underruns the input digital signal (IN), the phase detector 21 either provides ascending pulses (UP) with wider widths or descending pulses (DN) with narrow widths to the charge pump 22. At this time, the charge pump 22 generates a negative current output (Icp) that is integrated by the loop filter 23 to result in an ascending voltage (Vct) for controlling the voltage controlled oscillator 24 to raise the frequency of the reference clock signal (CLK) generated by the frequency divider 25. Therefore, through phase adjustment by the aforesaid phase-locked loop 2, the phase of the reference clock signal (CLK) will gradually converge to that of the input digital signal (IN) such that the current output (Icp) eventually reaches zero, which indicates a locked clock phase condition.
Nevertheless, since the record regions 11 and the header regions 12 may have blank areas with no data recorded therein, such as areas 121, 122 in a header region 12 and areas 111, 112 in a record region 11 as shown in FIG. 2, recorded areas of the DVDRAM 1 are actually discontinuous such that the clock phase fluctuates irregularly when reading the DVDRAM 1. As a result, the reference clock signal (CLK) from the frequency divider 25 will have a rather large phase difference with the input digital signal (IN), thereby requiring a relatively long amount of time for clock phase locking.